`timescale 1ns/1ps

module firstDemo_tb;

	reg clk,rst_n;
	
	wire [2:0] led;
	
	firstDemo #(.Tls(5)) dut(.clk(clk),.rst_n(rst_n),.led(led));

	initial
		begin
			clk=1;
			rst_n=0;
			#200.1
			rst_n=1;
			
			#2000 $stop;
		end
	always #10 clk=~clk;
	
endmodule
